Extending Boundary-Scan to Perform a Memory Built-In Self-Test

We present a novel test architecture which combines IEEE 1149.1 Boundary-Scan with a Memory Built-In Self-Test. The TDI pin is used for serially shifting in the test data into a test data register which is connected to the memory. The finite state machine of the TAP controller performs the memory test algorithm. The test response is shifted out via the TDO pin for off-chip analyses. The test architecture offers small area overhead, acceptable test time, increased flexibility and analysis capabilities while maintaining compliance to the Boundary-Scan standard.